As a high density, high capacity semiconductor memory, the DRAM (Dynamic Random Access Memory) is known. This DRAM includes a memory cell formed of one transistor and one capacitor. This memory cell has a structure in which a transistor M capable of being turned on/off depending upon a word line WL and a capacitor C are connected in series between a bit line (BL) and a common potential line (for example, a ground line GND). The memory cell records data using a difference in charge quantity stored on the capacitor. At the time of reading, a potential on a bit line is changed directly by the charge stored on the capacitor and the change is amplified by a sense amplifier to read whether stored information is “1” or “0.” In this DRAM, the charge stored on the capacitor gets away due to a leak current even in a state in which data is held (the transistor is in an off-state). Therefore, it becomes necessary to write back data periodically, i.e., to conduct operation of writing information which is read (hereafter referred to as refresh operation as well) periodically. It is required of the capacitor to be able to retain stored information for a given time (referred to as retention time as well) and have a capacitance capable of changing the potential on the bit line to an extent that the sense amplifier can read.
As the memory cell is miniaturized, however, it is necessary to make the area of the capacitor as well small and consequently it is becoming difficult to ensure the sufficient capacitance. Contrivances such as three-dimensional construction of the capacitor and use of a high dielectric as an insulation film have been made to secure the capacitance. As the generation advances, however, it is necessary to develop a new material and scaling is becoming difficult more and more.
Therefore, a two-transistor type DRAM having a configuration in which the capacitor is replaced with a transistor and charge is stored in a control electrode of the transistor and having a write transistor and a read transistor is proposed. On/off of the write transistor is controlled by a write word line, and charge is sent from a write bit line to the control electrode of the read transistor. At time of reading, it is distinguished whether information stored in the memory cell is “1” or “0” depending upon whether a current flows between a read bit line and a read word line. This two-transistor type DRAM is suitable for size shrinking in that it is formed of only transistors and it is not necessary to look for a new structure and a new material of the capacitor.
In this two-transistor type DRAM, however, a capacitor which stores charge is a gate capacitor of a transistor and its capacitance is small. As a result, the retention time is short and frequent refresh operations are required. Furthermore, normal reading cannot be conducted due to noise at times.